ADZS-BF533-EZLITE【PDF 17/64 页】KIT W/BOARD EVAL FOR ADSP-BF533

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ADSP-BF531 / ADSP-BF532 / ADSP-BF533

PIN DESCRIPTIONS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pin

definitions are listed in Table 9 .

All pins are three-stated during and immediately after reset,

except the memory interface, asynchronous memory control,

and synchronous memory control pins. These pins are all

driven high, with the exception of CLKOUT, which toggles at

the system clock rate. During hibernate, all outputs are three-

stated unless otherwise noted in Table 9 .

If BR is active (whether or not RESET is asserted), the memory

pins are also three-stated. All unused I/O pins have their input

buffers disabled with the exception of the pins that need pull-

ups or pull-downs as noted in the table.

In order to maintain maximum functionality and reduce pack-

age size and pin count, some pins have dual, multiplexed

functionality. In cases where pin functionality is reconfigurable,

the default state is shown in plain text, while alternate function-

ality is shown in italics.

Table 9. Pin Descriptions

Driver

Pin Name

Memory Interface

Type Function

Type 1

ADDR19–1

DATA15–0

ABE1–0/SDQM1–0

BR

BG

BGH

O

I/O

O

I

O

O

Address Bus for Async/Sync Access

Data Bus for Async/Sync Access

Byte Enables/Data Masks for Async/Sync Access

Bus Request (This pin should be pulled high if not used.)

Bus Grant

Bus Grant Hang

A

A

A

A

A

Asynchronous Memory Control

AMS3–0

ARDY

AOE

ARE

AWE

O

I

O

O

O

Bank Select (Require pull-ups if hibernate is used.)

Hardware Ready Control (This pin should be pulled high if not used.)

Output Enable

Read Enable

Write Enable

A

A

A

A

Synchronous Memory Control

SRAS

SCAS

SWE

SCKE

CLKOUT

SA10

SMS

O

O

O

O

O

O

O

Row Address Strobe

Column Address Strobe

Write Enable

Clock Enable (Requires pull-down if hibernate is used.)

Clock Output

A10 Pin

Bank Select

A

A

A

A

B

A

A

Timers

TMR0

TMR1/ PPI_FS1

TMR2/ PPI_FS2

I/O

I/O

I/O

Timer 0

Timer 1/ PPI Frame Sync1

Timer 2/ PPI Frame Sync2

C

C

C

PPI Port

PPI3–0

PPI_CLK/ TMRCLK

I/O

I

PPI3–0

PPI Clock/ External Timer Reference

C

Rev. I

|

Page 17 of 64 |

August 2013

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